Espressif Systems /ESP32-S2 /EXTMEM /CACHE_DBG_INT_ENA

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Interpret as CACHE_DBG_INT_ENA

Description

register description

Fields

CACHE_DBG_EN	The bit is used to activate the cache track function. 1: enable, 0: disable.
IBUS_ACS_MSK_IC_INT_ENA	The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.
IBUS_CNT_OVF_INT_ENA	The bit is used to enable interrupt by ibus counter overflow.
IC_SYNC_SIZE_FAULT_INT_ENA	The bit is used to enable interrupt by manual sync configurations fault.
IC_PRELOAD_SIZE_FAULT_INT_ENA	The bit is used to enable interrupt by manual pre-load configurations fault.
ICACHE_REJECT_INT_ENA	The bit is used to enable interrupt by authentication fail.
ICACHE_SET_PRELOAD_ILG_INT_ENA	The bit is used to enable interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations.
ICACHE_SET_SYNC_ILG_INT_ENA	The bit is used to enable interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations.
ICACHE_SET_LOCK_ILG_INT_ENA	The bit is used to enable interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations.
DBUS_ACS_MSK_DC_INT_ENA	The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.
DBUS_CNT_OVF_INT_ENA	The bit is used to enable interrupt by dbus counter overflow.
DC_SYNC_SIZE_FAULT_INT_ENA	The bit is used to enable interrupt by manual sync configurations fault.
DC_PRELOAD_SIZE_FAULT_INT_ENA	The bit is used to enable interrupt by manual pre-load configurations fault.
DCACHE_WRITE_FLASH_INT_ENA	The bit is used to enable interrupt by dcache trying to write flash.
DCACHE_REJECT_INT_ENA	The bit is used to enable interrupt by authentication fail.
DCACHE_SET_PRELOAD_ILG_INT_ENA	The bit is used to enable interrupt by illegal writing preload registers of dcache while dcache is busy to issue lock,sync and pre-load operations.
DCACHE_SET_SYNC_ILG_INT_ENA	The bit is used to enable interrupt by illegal writing sync registers of dcache while dcache is busy to issue lock,sync and pre-load operations.
DCACHE_SET_LOCK_ILG_INT_ENA	The bit is used to enable interrupt by illegal writing lock registers of dcache while dcache is busy to issue lock,sync or pre-load operations.
MMU_ENTRY_FAULT_INT_ENA	The bit is used to enable interrupt by mmu entry fault.

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